1. Technical Field
This invention relates to a process for realizing an integrated electronic circuit comprising two active layer portions with different crystal orientations. Such a circuit can be CMOS, or “Complementary Metal-Oxide-Semiconductor” in the terminology of a person skilled in the art. It also relates to an integrated electronic circuit of the type obtained by such a process.
2. Description of the Related Art
CMOS integrated electronic circuits contain MOS transistors with n-type conduction (nMOS) and MOS transistors with p-type conduction (pMOS).
The channel of a MOS transistor commonly has a monocrystalline portion based on silicon, to reduce the electrical resistance of the transistor in the on state. “Monocrystalline portion” is understood to mean a portion of crystalline material in which the crystal orientation does not substantially vary across this portion, in spite of the presence of any defects. Such defects may be dislocations or isolated defects for example.
It is also known that the electrical resistance of a MOS transistor channel depends on the crystal orientation of this channel. For a transistor which is intended to carry an electrical current by n-type carriers, the crystal orientation of the channel is preferably the crystallographic direction (1 0 0) of the silicon material, with a longitudinal conduction direction of the channel which additionally corresponds to a crystallographic direction (1 1 0) of the silicon. The crystallographic direction of the material is identified in the manner commonly used in crystallography, and two crystallographic directions are considered to be equivalent when they are associated by a symmetry operation of the crystal lattice. The crystal orientation of a portion of material in an integrated electronic circuit is defined by the crystallographic direction of this material which is perpendicular to the surface of the circuit substrate.
In a transistor which is intended to conduct an electrical current by p-type carriers, the crystal orientation of the channel which corresponds to a minimal electrical resistance is the crystallographic direction (1 1 0) of the silicon, with the longitudinal conduction direction of the channel parallel to a crystallographic direction (1 1 0) of the silicon again. In particular, the electrical resistance of the channel of a p-type conduction transistor can decrease by a factor of three when the crystal orientation of the channel is changed from (1 0 0), as in an n-type conduction transistor, to (1 1 0).
It is therefore particularly advantageous to realize the channels of nMOS and PMOS transistors of a CMOS circuit in different active layer portions which have the preferred crystal orientations for each type of transistor. To achieve this, various processes for realizing a CMOS circuit have been proposed, for combining monocrystalline active zones which have different orientations within the same circuit.
An “active zone” of an integrated electronic circuit is understood to mean a part of the circuit in which at least one transistor channel is realized or intended to be realized. In the text below, the material of an active zone is semiconducting and monocrystalline, silicon-based, and is doped in order to possess the appropriate electrical conduction.
In a first known process, a film based on monocrystalline silicon of orientation (1 1 0) is assembled with a silicon substrate of orientation (1 0 0). It is assembled by direct molecular bonding of the film's silicon material to the material of the substrate. Next the film material is rendered amorphous, then recrystallized in certain zones. The obtained recrystallization corresponds to the crystal orientation of the substrate. In this manner, active zones are available on the substrate which have the preferred crystal orientations for realizing pMOS and nMOS transistors. But these correspond to the bulk technology for realizing transistors, in which the transistors are isolated from the substrate by doping wells.
A second known process uses an SOI, for Silicon on Insulator, substrate. Such a substrate comprises a primary substrate based on monocrystalline silicon, an electrically insulating layer which is initially placed on a surface of the primary substrate, and an active layer based on monocrystalline silicon which is initially placed on the insulating layer. The primary substrate and the initial active layer have crystal orientations which respectively correspond to the crystallographic directions (1 0 0) and (1 1 0) of the silicon. The initial and insulating active layers are then selectively etched in a second zone of the substrate relative to a first zone of the substrate, so as to expose a surface of the primary substrate in the second zone. An insulating spacer is thus formed on the sides of the initial and insulating active layers between the first and second zones, then a portion of silicon is formed in the second zone by epitaxial growth, starting from the exposed surface of the primary substrate. In this way, active layer portions are obtained in the first and second zones which have the crystal orientations (1 1 0) and (1 0 0). They are therefore respectively adapted for realizing transistors with p-type and n-type conduction in these zones. The transistors in the first zone then correspond to the SOI technology, while those in the second zone correspond to the bulk technology. The integrated electronic circuit which is obtained is therefore a hybrid, making its design and fabrication more costly and difficult.
A third known process uses a dual-SOI substrate, with two superimposed active layers which are separated from the primary substrate by a first electrically insulating layer, and which are separated from each other by a second insulating layer. Each active layer is exposed in a different zone of the substrate, and has the crystal orientation adapted for one of the two types of transistors, p-type or n-type. But the dual-SOI substrate which is used is particularly costly because of its complexity.